2022-05-28.log

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* nsc -> Guest890303:39
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+ verx (~verx@matrix.16bit.dev)05:55
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+ littlebobeep (~alMalsamo@gateway/tor-sasl/almalsamo)06:04
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littlebobeep.09:14
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+ littlebobeep (~alMalsamo@gateway/tor-sasl/almalsamo)09:21
littlebobeepminute: I want to know what arcs spec is too09:27
littlebobeepcinap_lenrek: plz share09:27
+ littlebo1eep (~alMalsamo@gateway/tor-sasl/almalsamo)09:37
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- GNUmoon (QUIT: Ping timeout: 240 seconds) (~GNUmoon@gateway/tor-sasl/gnumoon)11:04
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+ littlebobeep (~alMalsamo@gateway/tor-sasl/almalsamo)16:16
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cinap_lenrek[ 6.866790] mixel-mipi-dphy 30a00300.dphy: 28 <= c7 # MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CM (/39)18:04
cinap_lenrek[ 6.866798] mixel-mipi-dphy 30a00300.dphy: 24 <= 1f # MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CN (0b11111==/1)18:04
cinap_lenrek[ 6.866805] mixel-mipi-dphy 30a00300.dphy: 2c <= 0 # MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC_DPHY_CO (0b00==/1)18:04
cinap_lenrek# DPHY input_clk * (CM / (CN * CO)) == REF_CLK (486MHz)18:04
cinap_lenrek# (12MHz) input_clk * (39 / (1 * 1)) == 486MHz. WRONG! input_clk should be 24MHz according to devicetree, and 12MHz is out of range!18:04
cinap_lenreki'm really confused whats going on here18:05
cinap_lenrektrying to start the dsi clock that afaik, is generated by the DSI DPHY18:05
cinap_lenrekthis is from register traces from linux18:05
cinap_lenrekbut the divider settings make no sense according to the RM18:06
- bkeys (QUIT: Remote host closed the connection) (~Thunderbi@static-198-54-135-37.cust.tzulo.com)18:06
+ bkeys (~Thunderbi@static-198-54-135-37.cust.tzulo.com)18:06
cinap_lenrekcould the divider tables in the RM be wrong?18:06
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minutecinap_lenrek: why don't they make sense? what's the correct refclk? 20:31
cinap_lenrekthats what i'm trying to determine20:32
minutemaybe 936 mhz? :D20:32
cinap_lenrekthats the thing, it programs 0x7 for the refclk register in the ti20:33
cinap_lenreksame as the colorbars "example" :)20:33
cinap_lenrekso i think it expects 486Mhz here20:33
minute486 should be fine20:34
cinap_lenrekyes20:34
cinap_lenrekalso, the dphy has a requirement that the input clock is >= 24MHz *after* input divider (CN)20:35
cinap_lenrekso 12Mhz makes no sense20:35
minuteaccording also to table 8-1 in sn65dsi86.pdf20:35
cinap_lenrekalso, theres a undocumented register write20:35
minutethere the clock is a multiple of 27mhz20:35
minute(486/18)20:36
minutei think that's also why you need to feed the 27MHz oscillator to the video system20:36
minutebut i could be remembering things wrong20:37
minutemaybe that was for hdmi...20:37
cinap_lenreki dont have hdmi device20:41
cinap_lenrekit is definitely turning on the lcd20:41
cinap_lenrekok20:41
cinap_lenreki give up now20:41
cinap_lenrekdev_dbg() doesnt work for me20:41
cinap_lenrekand i already wasted an hour recompiling everything without dynamic debug and force #define DEBUG20:42
cinap_lenrekbut also doesnt work20:42
cinap_lenrekso i'm just replacing with printk() now20:42
cinap_lenrekfuck this20:42
cinap_lenrek[ 6.841071] hs_clk/ref_clk=972000000/25000000 ~ 39/120:43
cinap_lenrek[ 6.841076] LP clock 20000000, period: 50000 ps20:43
cinap_lenrek[ 6.841081] phy_config: 0 0 9 30 11 11 720:43
cinap_lenrekso input clock is actually 25Mhz20:44
cinap_lenrekand the dsi clock then runs on 972Mhz20:44
cinap_lenrekwtf20:44
cinap_lenrekall the comments are always lies20:47
minutehm :3 25mhz sounds right. 25 and 27 are the two options IIRC20:50
cinap_lenrekthat is all very close so 486*220:50
cinap_lenrekwaiiit20:51
cinap_lenrekhow many lanes do we have?20:51
cinap_lenrekmaybe that value scales by the number of lanes or something?20:52
minuteshould be 4 lanes20:52
cinap_lenreki think i must have just confused myself20:56
cinap_lenrekmaybe theres no relation at all to the REFCLK frequency of the dsi2dp bridge20:57
cinap_lenrekto what is that REFCLK "pin" of the dsi2dp bridge wired up?20:58
cinap_lenreki should look at the schematics20:58
minutethe refclk pin is not wired up20:59
minutewe are using the second mode which is to derive the clock from the dsi a clock20:59
cinap_lenrekah20:59
minuteso sn will just sync to it20:59
minuteand we tell it what kind of freq to expect21:00
cinap_lenrekand it detects this automatically?21:00
cinap_lenrekor do we have to write 1 to the DPLL_CLK_SRC bit?21:01
cinap_lenrekU means for me its updated by hardware and readonly21:02
cinap_lenrekin any case, we write 0b11 to REFCLK_FREQ in that example, meaning Continuous DSIA CLK at 386MHz21:02
cinap_lenrek486 ;)21:03
cinap_lenrekas well as linux does the same21:03
cinap_lenrekbut it clearly uses a x39 multiplier to 25MHz refclock so gets 972MHz actually21:03
cinap_lenrekhow does that even work21:03
cinap_lenrekmaybe the DSIA CLK is REFCLK/2?21:04
cinap_lenreklike obviously for anyone who has read the dsi spec21:04
cinap_lenreksigrid → http://ftrv.se/_/refclkwat.png21:32
cinap_lenreksigrid nailed it21:32
cinap_lenrek"Since this is a DDR clocking scheme, the actual frequency is 792 MHz / 2"21:32
minutelol! ok!!21:50
minutegood to know btw21:50
minuteis that from the imx8mq ref manual? because it mentions an "SDK function" (??)21:50
sigridit's from an application note on mipi dsi21:51
sigridhttps://www.nxp.com.cn/docs/en/application-note/AN13573.pdf21:51
minuteah21:51
minutethanks!21:51
_Eminute: could you re-send the customs invoice for my RMA? the link from the ticket doesn't work21:52
cinap_lenreksigrid → ah right, https://www.nxp.com.cn/docs/en/application-note/AN13573.pdf is the doc that had that info21:52
cinap_lenrekarg21:52
cinap_lenrektoo late21:52
minute_E: sorry, i wonder why we didn't catch your question on friday21:53
_Eno problem, I just hope the shipping label hasn't expired after I made you all pay for it 😅️21:53
minutedoes not :)21:54
_Ethat's a relief21:55
_EI should be able to get the thing en route within a day or so, depending on my nearest UPS store's hours21:56
minutehmm i can't find your ticket atm, can you give me any keyword or reference number?22:06
minute(i'm at home)22:06
_Eminute: #105622:08
minute_E: thanks, found and sent the invoice via email manually22:12
minutecinap_lenrek: cool, reading this i finally understand LP and HS mode22:14
_Eminute: just arrived in my inbox, I'll get them printed off and attached, and the motherboard will be on its way22:14
minute_E: awesome22:14
+ vagrantc (~vagrant@2600:3c01:e000:21:7:77:0:20)23:08
- aliosablack (QUIT: Quit: Leaving) (~chomwitt@2a02:587:dc05:e000:eaa1:d30:2c04:8e84)23:22
- bkeys (QUIT: Remote host closed the connection) (~Thunderbi@static-198-54-135-37.cust.tzulo.com)23:38
+ bkeys (~Thunderbi@static-198-54-135-37.cust.tzulo.com)23:39
- mjw (QUIT: Quit: Leaving) (~mark@gnu.wildebeest.org)23:43
_Eah man, I forgot it was a holiday weekend23:43
_Eguess it's gonna be a couple days, then23:43
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+ bkeys (~Thunderbi@static-198-54-135-37.cust.tzulo.com)23:51

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