| - S0rin (QUIT: Ping timeout: 260 seconds) (~S0rin@user/s0rin) | 05:01 | |
| + S0rin (~S0rin@user/s0rin) | 05:03 | |
| Claude | minute, if you quickly want to mess around with PLLD (dsi) , I can assist you :) just needs /dev/mem and sone shell scripts I wrote | 08:14 |
|---|---|---|
| Claude | If that works out, you can probably stuff that into a dtoverlay too | 08:14 |
| Claude | It's a bit odd that the dsi bridge needs exactly 3*pixclock. | 08:15 |
| - S0rin (QUIT: Ping timeout: 264 seconds) (~S0rin@user/s0rin) | 09:39 | |
| + S0rin (~S0rin@user/s0rin) | 09:41 | |
| minute | Claude: thanks! i was thinking to ask you for some help today :D | 10:10 |
| minute | Claude: but i'll be only be back at the device in the afternoon | 10:11 |
| minute | Claude: the sn65dsi86 doesn't care much about the pixelclock i think, but if i understand correctly there are only a limited number of valid dsi refclks. the display wants 162 mhz pixclk / 486 mhz refclk | 10:14 |
| minute | but the pi selects 166 mhz / 498 (need to double check if this is true) which then results in failing dp training in the bridge (actually not sure if it fails dp or dsi link training, but i think dp). | 10:16 |
| minute | the next step down it can do is 125 mhz. with that i can get flashing color bars with the bridge's color bar test mode. not sure why the timing is broken then. it's possible that 125 is already too low for the display. | 10:17 |
| minute | IIRC actually i was able to go down to very low pixelclocks using the kintex fpga+analogix edp encoder (like 80mhz?) | 10:19 |
| minute | i guess the tricky part is that the sn65dsi86 needs to recover its clocks from the dsi refclk. if it can't lock to that, everything goes wrong | 10:22 |
| minute | > MIPI D-PHY channel A clock lane; operates up to 750 MHz. Under proper conditions, this clock can be used instead of REFCLK to feed DisplayPort PLL | 10:54 |
| minute | Claude: yeah so the thing is that i didn't use a dedicated refclk for the DP portion of the bridge, so it has to be recovered from DSI A, and for that only the following clocks are allowed: 384,416,468,486 or 460.8. so i need to get the pi to use one of these frequencies for dsi. | 10:59 |
| minute | this is also a bit wonky https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/vc4/vc4_dsi.c#L902 | 11:06 |
| minute | Claude: but if i understand correctly the driver gets the dsi clock by just multiplying the pixel clock of the mode by a fixed factor (dsi->divider) | 11:08 |
| minute | dsi->divider is 6 for 24bpp, 4 lanes i think | 11:10 |
| minute | Claude: ideally i would need to tune PLLD down to 2916000000 hz, do you think that's possible? | 11:11 |
| minute | alternatively 2.808ghz or 2.7648ghz or 2.49599...ghz | 11:13 |
| minute | actually i'm not sure if clk_get_parent(dsi->pll_phy_clock) is PLLD directly or something in between, but as it is 3ghz i figured it is PLLD | 11:27 |
| minute | yup https://forums.raspberrypi.com/viewtopic.php?p=1668620&sid=d13f64c07ebf39b25a9871cd6590ca48#p1668620 | 11:28 |
| minute | ironic that 54mhz * 3 = 162 :( | 11:28 |
| minute | > Clocks are a juggling nightmare in the firmware. A couple of years ago I was trying to get a DSI->HDMI bridge chip going, and getting the clocks right for that meant all sorts of pain elsewhere in the system - I think it killed composite or something. We gave up in the end. Just not enough clocks to go round, along with other issues | 11:59 |
| minute | quote by "jamesh" @ rpi from the forum | 11:59 |
| Claude | Minute, currently still at work . When I get home this evening I look for the pll scripts | 12:35 |
| Claude | Also handy for beyond insane OC on cm4 ;) | 12:35 |
| Claude | Stupid firmware limits the pll to punny 2.5GHz | 12:36 |
| minute | nice, thanks | 12:38 |
| - S0rin (QUIT: Read error: Connection reset by peer) (~S0rin@user/s0rin) | 17:34 | |
| + S0rin (~S0rin@user/s0rin) | 17:51 | |
| minute | Claude: ping (sorry to be a bother!) | 19:59 |
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