| - S0rin (QUIT: Ping timeout: 252 seconds) (~S0rin@user/s0rin) | 00:46 | |
| + S0rin (~S0rin@user/s0rin) | 00:52 | |
| - S0rin (QUIT: Ping timeout: 252 seconds) (~S0rin@user/s0rin) | 01:07 | |
| + S0rin (~S0rin@user/s0rin) | 01:10 | |
| - neoman (QUIT: Ping timeout: 260 seconds) (~neoman@titandemo.org) | 01:43 | |
| + neoman (~neoman@titandemo.org) | 01:44 | |
| + Jadek (~Jadek@87-207-204-28.dynamic.chello.pl) | 09:35 | |
| _Bnu | Chain^Q: There's a hole? Do you mean make it enumerate the Fast RAM first and then the RTG, so it's continuous with the BigRAM? | 12:52 |
|---|---|---|
| _Bnu | My first instinct is to say "Stop *** using Z3 Fast RAM, it's slow as shit", but. | 12:52 |
| _Bnu | Of course it could be done that way, you just have to swap which one is enumerated first in the Verilog. | 12:53 |
| Chain^Q | Sure. But I'm not sure if that does more harm than good, because it also depends on the order of cards in the machine, of course. | 12:55 |
| Chain^Q | And I'm not _actually_ trying to use this ram :) just had some fun with it | 12:56 |
| Chain^Q | under the order of cards I mean, I'm trying this in my 4000T, but I have no idea if the slots are enumerated the same or in the reverse order say in a 4000D, let alone a 3000. | 12:56 |
| Chain^Q | but for my own fun, sure I could swap them in the Verilog | 12:57 |
| _Bnu | As far as I know, they're always enumerated from bottom to top, but it could be different on some other daughterboards I suppose. | 15:50 |
| _Bnu | Well, top to bottom in an A4000T. From start to end. | 15:51 |
| _Bnu | (As long as it's an actual A4000T motherboard.) | 15:51 |
| - Jadek (QUIT: Quit: Connection closed) (~Jadek@87-207-204-28.dynamic.chello.pl) | 18:44 | |
Generated by irclog2html.py 2.17.3 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!