| - xet7 (QUIT: Quit: Leaving) (~xet7@user/xet7) | 00:45 | |
| + xet7 (~xet7@user/xet7) | 00:46 | |
| + mntamiga (~amiga3000@p54a43c5a.dip0.t-ipconnect.de) | 13:10 | |
| mntamiga | testing some ZZ9000s | 13:10 |
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| mntmn | mntamiga: woop doot | 13:10 |
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| apolkosnik[m] | Nice | 14:08 |
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| + xet7 (~xet7@user/xet7) | 17:26 | |
| _Bnu | mntmn: Did you keep any ZYNQs to make a ZZ3660... | 19:47 |
| mntmn | _Bnu: nope, also isn't that using z-turn? | 19:56 |
| mntmn | or did shanshe change it? | 19:56 |
| _Bnu | Ah yeah, the Z3660. | 20:05 |
| _Bnu | But you did say that you wanted to design one that used the other ZYNQ module, I was just reminded when I saw your post on Twitter, haha. | 20:06 |
| mntmn | haha i said i would perhaps collaborate on one, yes | 20:07 |
| mntmn | did shanshe publish the design files? | 20:07 |
| mntmn | github has gerber+schematics | 20:08 |
| mntmn | anyway, can't really start a new project now, we have enormous backlog | 20:08 |
| mntmn | almost 100 zzs still to send out and the carrier boards are not produced yet, and 350 z9ax to ship and also AHI sampling still to implement | 20:08 |
| mntmn | and jpeg+mp3 to do for zz :3 | 20:08 |
| mntmn | so enough in the pipeline | 20:08 |
| shanshe | hi, Z3660 design files are published, but still is the first version | 20:09 |
| shanshe | I want to fix some things before | 20:09 |
| mntmn | nice | 20:10 |
| mntmn | hmm looks almost like it's getting a bit better https://www.mouser.de/ProductDetail/MYIR/MYC-C7Z020-4E1D-766-I?qs=%2Fha2pyFaduj2Ujj63BMrLKl2Pb04gx4doejnxRtTggE%3D | 20:11 |
| shanshe | yeah z-turn is also reprogrammed for the same date | 20:12 |
| shanshe | but I could buy one in aliexpress, and now is going to Bnu's home :) | 20:13 |
| mntmn | alright! | 20:13 |
| shanshe | I can't get more than 56 MB/s | 20:13 |
| shanshe | from RAM | 20:13 |
| shanshe | so maybe I will try to put some RAM in the same Z3660 board | 20:14 |
| shanshe | some SDRAM I mean | 20:14 |
| shanshe | but for now, I don't have so much time for Amiga. I need two consecutive holidays to update all delayed work... hehehe | 20:17 |
| shanshe | also, not in this current version, but I want publish kicad files... so if you want we can try to change zturn to zz9000 module (so we could change the name from Z3660 to ZZ3660 hehehe) | 20:21 |
| mntmn | haha i feel ya | 20:22 |
| shanshe | other people pointed me to change the design to support 040, but I don't know what to do in this way... | 20:22 |
| mntmn | shanshe: and yeah that would be cool @ doing a spin with the zynq module, so people could side-grade | 20:23 |
| mntmn | (the module is the MYC-C7Z020 btw) | 20:24 |
| shanshe | wow now I remember... | 20:25 |
| shanshe | I was talking with a Spanish guy that is making a 1260 board... | 20:26 |
| shanshe | I he said that it is very easy with the 060 to change to another master bus... so probably, we could use ARM 68k emulation, and this way you don't need a 060 | 20:27 |
| shanshe | so we could make a super cheap board without 060, and 68k emulation like pistorm | 20:28 |
| shanshe | but if you want the real thing, then you buy one 060 for 350 euros hehehe | 20:29 |
| shanshe | then you don't need to spend a lot at once, so you could buy this board and FPGA | 20:30 |
| shanshe | and then when you can, buy a 060 | 20:30 |
| mntmn | do you have the zynq on the same bus? | 20:32 |
| mntmn | (i guess you must have) | 20:32 |
| shanshe | yes | 20:32 |
| shanshe | this guy, stops the 060 and send cycles from the debug system (he doesn't have an ARM) | 20:33 |
| mntmn | trying to understand how your level shifters / buffers work | 20:33 |
| mntmn | each has 6 control signals? | 20:34 |
| shanshe | it is the same than A3660 | 20:34 |
| shanshe | there are latches for the data bus | 20:34 |
| shanshe | and pull down resistors for address bus | 20:35 |
| mntmn | ah there is a cpld driving all that? | 20:35 |
| shanshe | yes | 20:35 |
| shanshe | CPLD is replacing almost all logic from A3660 | 20:35 |
| shanshe | and 060 data and address bus is directly to FPGA | 20:36 |
| shanshe | without any multiplexer... so I have only a few control signals on FPGA | 20:37 |
| mntmn | ah the 060 is 3.3v anyway, right | 20:37 |
| shanshe | yeah | 20:37 |
| shanshe | there is only a drawback | 20:37 |
| shanshe | when you reset, the address bus is tristated | 20:37 |
| mntmn | ok? | 20:38 |
| shanshe | and on mobo there is a pullup on address bus | 20:38 |
| shanshe | that raises the bus to 5V | 20:38 |
| mntmn | eek | 20:38 |
| shanshe | so I put pulldown resistors to make a voltage divider | 20:38 |
| mntmn | oof | 20:38 |
| shanshe | those resistor are not in the first schematics | 20:39 |
| mntmn | i see | 20:39 |
| mntmn | so each reset the fpga is smoked a bit | 20:39 |
| mntmn | tiny bit | 20:39 |
| mntmn | gently roasted | 20:39 |
| shanshe | no | 20:39 |
| mntmn | ;) | 20:39 |
| shanshe | the voltage never is higher than 3.3 volts | 20:40 |
| shanshe | but yeah, probably in the next version I should put there some CBT bus transceivers... | 20:41 |
| mntmn | ok ok | 20:50 |
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